Capacitor having a tantalum lower electrode and method of forming the same

ABSTRACT

A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a capacitor having a tantalumlower electrode and a method of fabricating the same.

[0003] 2. Background of the Related Art

[0004] Capacitors are found in numerous semiconductor devices. Despitethe proliferation of various types of capacitors, large amounts ofeffort are still expended in attempts to obtain capacitors that haveparticular electrical characteristics and can also be easily fabricatedusing modem semiconductor fabrication technologies.

[0005] One specific capacitor of this type that has been proposed is acapacitor that uses tantalum to form its lower electrode. For example,U.S. Pat. No. 5,142,438 describes such a capacitor. This lowerelectrode, through buried contacts, electrically connects to the wordand bit lines of a semiconductor DRAM memory. The tantalum layer isthereafter subjected to a rapid thermal processing or furnace heatingwhich creates a tantalum silicide layer at the tantalum layer'sinterface with the silicon substrate, and an insulating tantalumpentoxide dielectric layer at the top of the tantalum layer. Afterdepositing a layer of barrier material such as silicon nitride, apolysilicon electrode layer is deposited on the structure and doped.

[0006] While the above-described approach allows for the creation of adielectric layer over a conducting layer without specifically applying adistinct dielectric layer, the applications in which this device can beused are limited due to a number of considerations.

[0007] For example, when the capacitor is used in a DRAM as disclosed inthe '438 patent, its charge storage need not be very great. Accordingly,the very thin tantalum pentoxide layer that is formed can be used.Consequently, a correspondingly thin deposited tantalum layer can beused to form the tantalum pentoxide layer. If, however, a thickertantalum pentoxide layer was needed in order to allow for greater chargestorage, a thicker original tantalum layer would be used. This cannot,however, be easily achieved, since thick tantalum layers are known toexhibit stress characteristics that lead to warpage of the wafer onwhich it is formed.

SUMMARY OF THE INVENTION

[0008] The present invention is made with the above-mentioned problemsof the prior art in mind, and it is an object of the present inventionto provide a capacitor which can be fabricated on a semiconductorsubstrate using semiconductor fabrication techniques to provide highcapacitance while consuming reduced chip area.

[0009] It is a further object of the invention to provide such acapacitor which has switching characteristics variable according toparameters of the fabrication process.

[0010] It is yet another object of the invention to provide such acapacitor which can perform a non-volatile charge storage function.

[0011] The above objects are achieved by forming a capacitor in which,according to a first preferred embodiment of the invention, a titaniumnitride layer is deposited on a silicon substrate for stress reductionand adherence promotion, and a layer of tantalum is deposited thereon.Then, the tantalum layer is oxidized using a furnace or RTA to produce atantalum pentoxide layer. A top electrode of metal or polysilicon isthen deposited on the tantalum pentoxide layer.

[0012] According to one aspect of the invention, the top electrode ismade from polysilicon or a similar semiconducting material so that aspace charge layer will form in the electrode which will change the rateat which the capacitor charges and discharges. Other fabricationparameters described in greater detail herein also affect the chargingcharacteristics of the resultant capacitor.

[0013] According to another aspect of the invention, the top electrodeis preferably made from metal to provide an optimal linear response foruse in analog applications. An appropriate application for a capacitordesigned in this way would be for tuning a receiver circuit or the like.

[0014] According to yet another aspect of the present invention, anundoped polysilicon layer above the tantalum pentoxide layer between thetop and bottom electrodes stores charge for non-volatile memoryapplications. For this purpose, polysilicon can be used to form the topelectrode; alternatively, materials such as silicon nitride may be used.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] These and other objects, features, and advantages of the presentinvention are better understood by reading the following detaileddescription of the preferred embodiments, taken in conjunction with theaccompanying drawings, in which:

[0016] FIGS. 1-4 are cross-sectional diagrams of a semiconductor chipshowing the steps in fabricating a capacitor according to a firstpreferred embodiment of the present invention;

[0017]FIG. 5 is a graph showing the effect of dopant levels in apolysilicon layer in the first preferred embodiment;

[0018]FIGS. 6 and 7 are cross-sectional diagrams of a semiconductor chipshowing the additional steps in fabricating a capacitor according to asecond preferred embodiment of the present invention;

[0019]FIG. 8 is a diagram showing a tunneling effect according topreferred embodiments of the present invention;

[0020] FIGS. 9A-9E show an embodiment of the present invention used as astandalone unit next to a transistor;

[0021] FIGS. 10A-10C show an embodiment of the present invention used inconjunction with a transistor; and

[0022] FIGS. 11A-11C show an embodiment of the present invention inwhich an oxide blocking mask is used to prevent interaction of TiN withsilicon.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EXEMPLARY EMBODIMENT

[0023] To form a capacitor 100 according to a first preferred aspect ofthe present invention, a titanium nitride layer 20 to provide stressreduction and promote adherence of the layer above it for the resultantcapacitor 100 is deposited, preferably to a thickness of at least 50 Åbut possibly greater than 1 μm) on a silicon substrate 10 as shown inFIG. 1.

[0024] The silicon substrate is preferably doped with N or P typedopant. This doped region may extend out from under the capacitor and beconnected to other transistors or resistors.

[0025] Further, the titanium nitride layer 20 provides stress relief asfollows. The stoichiometry (Ti-to-N ratio) of the layer 20 controls thedensity or atomic bonding distance of the titanium nitride layer 20 andits strength. When titanium nitride is in contact with silicon and heatis applied, there is an interaction of the titanium nitride layer 20with the silicon substrate 10 where the titanium nitride bond breaks,releasing nitrogen, and the titanium combines with the silicon.

[0026] Since stress in a film is due to the change in the atomic bondingdistance between its components, when two different materials withdifferent atomic bonding distances are interposed, the resultantintermixing of the two films results in either a contraction orexpansion of this distance. The thickness and strength of one materialcompared to another determines the extent to which each material willdeform. So, controlling the thickness of the titanium nitride layer 20relative to the tantalum layer 30 and the density of the titaniumnitride layer 20 will control the resultant stress of the titaniumnitride/tantalum films 20 and 30 relative to the silicon substrate 10.

[0027] The titanium nitride layer 20 is preferably deposited usingphysical vapor deposition (PVD) at a temperature anywhere from roomtemperature to 500° C. Also, this titanium nitride layer 20 may bedeposited using techniques to control the direction of the incoming ionsby IMP (inductively coupled plasma) or long throw (long distance fromtarget to wafer surface) to control orientation of the titanium nitridefilm (a <111> orientation is preferred) for a dense titanium nitridelayer 20. The preferred temperature of titanium nitride deposition is150° C. using IMP for about 10 seconds.

[0028] Next, as shown in FIG. 2 a layer of tantalum 30 is deposited onthe tantalum nitride layer 20, preferably to a thickness of at least 50Å but possibly greater than 1 μm. Then, the tantalum layer 30 isoxidized using a furnace or rapid thermal oxidation to grow a tantalumpentoxide layer 40, preferably to a thickness of 20-5000 Å as shown inFIG. 3.

[0029] The rapid thermal oxidation can be done at a temperature between600° C. to 1000° C., but preferably is performed at 800° C. in anambient oxygen atmosphere. After the growth of the tantalum pentoxidelayer 40, it can be densified in a nitrogen (or an inert gas) ambient atabout 900° C., or more preferably 960° C. The thickness of the tantalumpentoxide layer 40 depends on the capacitor characteristics needed, aswill be readily apparent to those skilled in the art.

[0030] The thickness of the tantalum pentoxide layer 40 is controlled bythe size of the capacitor. Tantalum pentoxide has a dielectric constantthat is four times higher than silicon dioxide, which means (compared tosilicon dioxide) the area of the layer 40 can shrink or the dielectricthickness can increase by four times. In order to make use of thefourfold increase in dielectric constant of tantalum pentoxide oversilicon dioxide, an equivalent tantalum pentoxide layer 40 gatethickness of 200 Å is preferred.

[0031] A top electrode 50 of metal or polysilicon is then deposited asshown in FIG. 4. With this structure, the top electrode 50 and tantalumlayer 30 serve as electrodes for connecting the capacitor 100 to othercircuitry on the semiconductor chip, i.e., word and bit lines, etc.

[0032] The top electrode 50 can be deposited using PVD or CVDtechniques. The temperature of the deposition should be in the range ofroom temperature to 600° C. The preferred embodiment uses titaniumnitride PVD at 200° C.

[0033] Thus, in the above manner, although not requiring a separateprocess step for its deposition, the tantalum pentoxide layer 40 servesa high-level, high-quality dielectric layer, and the titanium nitridelayer 20 relieves stress induced by the fabrication of the layers aboveit.

[0034] The top electrode 50 can be a metal such as tantalum, asemiconductor material such as polysilicon, or a combination of the two.The composition of the top electrode 50 influences the linearity andswitching speed of the capacitor 100 in both analog and memoryapplications.

[0035] For example, if polysilicon and tantalum were used for the topelectrode 50, polysilicon's resistance would control the timing delaytargeting information in and out of the circuit in which the capacitor100 is employed. If the current from the capacitor 100 passed throughthe polysilicon, then the combination of the polysilicon resistance withthe rate at which the space charge layer within it collapsed wouldcontrol the timing delay (τ≈RC) of the circuit. The tantalum layer 30above the electrode layer 50 would be another barrier during the contactetch. Prolysilicon could be used for only the top electrode 50 since thelower tantalum electrode 40 is being oxidized to produce tantalumpentoxide for the capacitor's dielectric. The dielectric constant of thecapacitor would be a combination of those of both the tantalum pentoxideand polysilicon.

[0036] If the top electrode 50 is made from polysilicon or a similarsemiconducting material, then-as noted above a space charge layer willform in the electrode 50, which will change the rate at which thecapacitor 100 charges and discharges. Further, the resistance of thepolysilicon is controlled by its dopant concentration, film thicknessand grain structure, all of which will have an influence on R in theτ=RC timing delay. The doping concentration would offer the most precisecontrol of the resistance of the polysilicon line. The doping of theelectrode 50, its dopant profile, concentration and polysilicon grainstructure will influence the depth of the space charge layer and thecapacitor's electrical response characteristics.

[0037] The direction in which the capacitor 100 is biased (generally, apositive potential would be applied to the polysilicon or electrode sideof the capacitor) will also have a major influence on the space chargelayer formed in the electrode layer 50 and the capacitor 100 responsecharacteristics, meaning it will take a longer time for the capacitor100 to charge and discharge in a bias direction of one polarity comparedto the bias direction of the opposite polarity. This effect is dependenton frequency, which is associated with the mobility difference of theelectrons or holes in the thickness of the space charge region in thesemiconductor, as well as the dopant type in the polysilicon (P or N).So, the linearity of the capacitance, i.e., dC/dV—the change incapacitance relative to voltage, can be tailored by appropriate designof the capacitor 100.

[0038] A capacitor 100 designed in this way would act like twocapacitors in series with a resistor, thereby forming an RC timingcircuit. More specifically, the dC/dV characteristic is controlled bythe capacitance of the space charge region in the electrode layer 50which is controlled by the dopant concentration. The effective circuitconsists of a resistor (formed by series resistances of the polysiliconand tantalum in the electrode layer 50) which can be controlled bydopant level therein, in series with two series-connected capacitors(one being formed from a space charge region in the electrode layer 50and the other from the tantalum pentoxide dielectric layer 40).Additional series resistances are formed by the tantalum layer 30 andthe titanium nitride or TiSi₂ layer 20. So, changing the dopant levels,dopant profiles and activation level in the electrode layer 50 controlsthe polysilicon resistor and space charge capacitance.

[0039] As shown in the graph of FIG. 5, using N or P type dopants alongwith nitrogen can independently control these values. Nitrogen does notdiffuse as quickly in the polysilicon and interferes with theincorporation of the N or P type dopant into the polycrystallinestructure. Therefore, nitrogen would control the resistance locally atthat interface where the space charge region is formed. If nitrogen isnot used then just controlling the dopant level and concentration of Por N type dopants would have the same effect.

[0040] When the capacitor 100 is used in analog applications, bothelectrodes need to be metal to eliminate the space charge layer, whichimproves switching speed, linearity—change in capacitance vs. voltageshould be as constant, flat, as possible over the entire voltagerange—and the tantalum pentoxide free of fixed charge to get the bestlinear response, i.e., no change in capacitance relative to voltage. Anappropriate application for a capacitor 100 designed in this way wouldbe for tuning a receiver circuit or the like.

[0041] According to a second preferred embodiment of the presentinvention as shown in FIGS. 6 and 7, it is possible to include anundoped polysilicon layer 60 above the tantalum pentoxide layer 40between the top and bottom electrodes 20 and 50 as shown in FIGS. 6 and7 and then deposit an insulating layer 70 of, e.g., silicon dioxide, onit (see FIG. 7) before depositing the top electrode 50, thereby forminga capacitor 200 which stores charge for non-volatile memoryapplications.

[0042] In this embodiment, electrodes either tunnel through the tantalumpentoxide layer 40 or insulator layer 70 to deposit and trap changes inthe polysilicon layer 60, which could alternatively be Si₃N₄ or a dopedpolysilicon layer. Metal electrodes, polysilicon, silicide or acombination of electrodes can be used. When voltage is applied in onedirection, tunneling occurs to charge the polysilicon; when the voltageis off, then the quality of the oxide (leakage characteristics) controlsthe discharge rate. The tunneling dielectric has to be thin and of highquality, so silicon dioxide is preferred.

[0043] For this purpose, undoped polysilicon can be deposited on thetantalum pentoxide layer 40; alternatively, materials such as siliconnitride may be used. If polysilicon is used, it can be oxidized to forma high quality oxide above to be in contact with the top electrode. ForSi₃N₄ this oxide has to be deposited, then annealed.

[0044] For non-volatile memory applications, the necessary thickness ofthe tantalum pentoxide layer 40 is related to the operating voltage ofthe chip, and determines the voltage at which tunneling current wouldoccur in the capacitor 200. This is because Fowler-Nordheim tunnelingcurrent occurs before avalanche breakdown of the dielectric as shown inFIG. 8. Therefore, the thickness needs to be precisely controlled to arange of +/−5% or 5 Å.

[0045] For a non-volatile memory application, electrons tunnel throughthe tantalum pentoxide layer 40 and are trapped in the undopedpolysilicon or silicon nitride layer 60 to establish non-volatile chargestorage. To dissipate the stored charge, the bias of capacitor 200 isreversed.

[0046] More specifically, after forming the tantalum layer 30 andtantalum pentoxide layer 40 as described above, he polysilicon isdeposited at 510° C.-680° C. (preferably 620° C.) to a thickness of 5 Åto 3000 Å (preferably 100 Å). The oxide is preferably deposited by ahigh temperature, low pressure HTO process (reduction of SiH₄ with O₂ ina CVD tube) to deposit a 10 Å to 100 Å (preferably 60 Å) oxide for a 5Vprocess (or preferably 40 Å for a 3.3 V process). This oxide could alsobe deposited by a PECVD or HDP process using the same source gases.

[0047] The oxide is annealed in a furnace in nitrogen at 900-1080° C.(preferably 950° C.) for 5 minutes to 4 hours (preferably 20 minutes).The preferred method is to deposit a thicker polysilicon film, thenoxidize it at 850-1050° C. (preferably 900° C.) in a O₂ ambient. Thisoxide would be grown to the same tunneling thickness as stated before.The operation consists of biasing the entire stack such that the voltagedrop across the tunneling dielectric reaches an E field level whereFowler-Nordheim tunneling would occur. Most of the voltage drop acrossthe stack will occur across the SiO₂ film.

[0048] A single nonvolatile cell consists of stacked layers and thecells are in parallel. Thus, the use of a higher k oxide is needed toreduce the size of these capacitor elements. Accordingly, oxides such asTa₂O₅, are preferred.

[0049] FIGS. 9A-9E show an embodiment of the present invention used as astandalone capacitor. In FIG. 9A, the TiN and Ta have been deposited andRTP of the Ta has been completed to form Ta₂O₅. Additionally, thedeposition of the top electrode material has been completed. In FIG. 9B,the capacitor has been defined using photolithographic techniques. InFIG. 9C, the structure has been etched to remove the capacitor layers.Here, the transistor layer could be blocked from TiN reaction withexposed silicon by an oxide hard mask requiring separate deposition andphotolithography (not shown). FIG. 9D shows the addition of aphotoresist strip, and FIG. 9E shows the deposition of oxide andplanarization of the oxide face using CMP.

[0050] FIGS. 10A-10C show another embodiment of a capacitor-transistordesign where the transistor may be used to charge the capacitor. Here,starting with the structure of FIG. 10A, FIG. 10B shows the structureafter tungsten plug fill and polish, and FIG. 10C shows the resultantstructure after metal 1 deposition, photolithography and etching.

[0051] Finally, FIGS. 11A-11B show another embodiment of the presentinvention employing an oxide blocking mask preventing interaction of theTiN with the silicon surface. Here, FIG. 11 A shows the structure afterdeposition of TiN and Ta films. FIG. 11B shows the resultant structureafter RTP oxidation of the Ta layer to form Ta₂O₅. Implant activationmay also be performed here. Finally, FIG. 11C shows the formation of theblocking mask.

[0052] The present invention has been described above in connection witha preferred embodiment thereof; however, this has been done for purposesof illustration only, and the invention is not so limited. Indeed,variations of the invention will be readily apparent to those skilled inthe art and also fall within the scope of the invention.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; a tantalum layer disposed on a first side ofthe semiconductor substrate; a tantalum pentoxide layer disposed in thetantalum layer; and an electrode layer disposed onto a side of thetantalum pentoxide layer opposite the semiconductor substrate.
 2. Thedevice of claim 1, wherein: the tantalum layer serves as an electrode ofthe device; and the tantalum pentoxide layer serves as a dielectriclayer of the device.
 3. The device of claim 1, further comprising alayer disposed between the semiconductor substrate and the tantalumlayer for providing at least one of a stress reduction effect and anadherence effect to the semiconductor substrate and the tantalum layer.4. The device of claim 1, wherein the electrode layer is a metal.
 5. Thedevice of claim 1, wherein the electrode layer is polycrystallinesilicon.
 6. The device of claim 5, further comprising a nitrogen dopingat an interface between the tantalum pentoxide layer and thepolycrystalline silicon layer to control the resistance of a spacecharge layer formed therein when the device is operational.
 7. Asemiconductor device comprising: a semiconductor substrate; a tantalumlayer disposed on a first side of the semiconductor substrate; atantalum pentoxide layer disposed in the tantalum layer; an electrodelayer disposed on a side of the tantalum pentoxide layer opposite thesemiconductor substrate; a semiconductor layer disposed between thetantalum pentoxide layer and the electrode layer; and an insulatinglayer disposed between the semiconductor layer and the electrode layer.8. The device of claim 7, wherein: the semiconductor layer is capable ofperforming non-volatile charge storage; and the insulating layerinsulates the semiconductor layer from the electrode layer.
 9. Thedevice of claim 7, wherein the semiconductor layer is silicon nitride.10. The device of claim 7, wherein the semiconductor layer ispolycrystalline silicon.
 11. The device of claim 10, further comprisinga nitrogen doping at an interface between the tantalum pentoxide layerand the polycrystalline silicon layer to control the resistance of aspace charge layer formed therein when the device is operational.
 12. Amethod of fabricating a semiconductor device comprising: depositing alayer of tantalum proximate to a first side of a semiconductorsubstrate; growing a tantalum pentoxide layer in the tantalum layer; anddepositing an electrode layer onto the tantalum pentoxide layer.
 13. Themethod of claim 12, further comprising depositing a layer of titaniumnitride on the semiconductor substrate, the tantalum layer beingdeposited on the titanium nitride layer.
 14. The method of claim 12,wherein the electrode layer is deposited on the tantalum pentoxidelayer.
 15. The method of claim 12, wherein the electrode layer is ametal.
 16. The method of claim 12, wherein the electrode layer ispolycrystalline silicon.
 17. The device of claim 16, further comprisingdoping nitrogen at an interface between the tantalum pentoxide layer andthe polycrystalline silicon layer to control the resistance of a spacecharge layer formed therein when the device is operational.
 18. A methodof fabricating a semiconductor device comprising: depositing a layer oftantalum proximate to a first side of a semiconductor substrate; growinga tantalum pentoxide layer in the tantalum layer; depositing asemiconductor layer on the tantalum pentoxide layer; and depositing aninsulating layer on the semiconductor layer; and depositing an electrodelayer onto the tantalum pentoxide layer.
 19. The method of claim 18,wherein the semiconductor layer is silicon nitride.
 20. The method ofclaim 18, wherein the semiconductor layer is polycrystalline silicon.21. The device of claim 20, further comprising doping nitrogen at aninterface between the tantalum pentoxide layer and the polycrystallinesilicon layer to control the resistance of a space charge layer formedtherein when the device is operational.